Kumar Yelamarthi

Department of Engineering and Technology, Central Michigan University, Mount Pleasant, Michigan 48859, United States of America.
Tel: +1 989 774 7164
Email: kumar.yelamarthi@cmich.edu
Web: www.et.cmich.edu/case/CASE/CASE.html

Interests

Kumar Yelamarthi's teaching areas include: Digital design, VLSI systems, analog and mixed-signal circuits, microprocessors, freshman programs and interdisciplinary senior design projects.

Current projects

Smart Cane for the Blind Using RFID

Publications

Martin, W., Dancer, K., Rock, K. Zeleny, C. & Yelamarthi, K. (2009) The Smart Cane: an electrical engineering design project. Proceedings of ASEE North Central Section Conference, Michigan, USA, 3-4 April 2009.

Yelamarthi, K. & Chen, C-I. H. (2008) A path oriented in time optimization flow for mixed-static-dynamic CMOS logic. Proceedings of 51st IEEE Midwest Circuits and Systems Conference, Tennessee, USA, 10-13 August 2008.

Yelamarthi, K. & Chen, C-I. H. (2008) Process variation aware transistor sizing for load balance of multiple paths in dynamic CMOS for timing optimization. Journal of Computers, 3(2), 21-28.

Yelamarthi, K. & Chen, C-I. H. (2008) Process variation aware timing optimization through transistor sizing in dynamic CMOS logic. Proceedings of IEEE International Symposium on Quality Electronic Design, , California, USA, 17-19 March 2008.